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FUJITSU SEMICONDUCTOR DATA SHEET
DS05-50102-2E
MCP (Multi-Chip Package) FLASH MEMORY
CMOS
8M (x 8/x 16) FLASH MEMORY & 8M (x 8/x 16) FLASH MEMORY
MB84VB2000-10/MB84VB2001-10
s FEATURES
* Contain 2 chips of MBM29LV800A, and each chip have separate CE. * Power supply voltage of 2.7 to 3.6 V * High performance 100 ns maximum access time * Operating Temperature -40 to +85C * Minimum 100,000 write/erase cycles * Sector erase architecture One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes x 2 chips Any combination of sectors can be concurrently erased. Also supports full chip erase. * Boot Code Sector Architecture MB84VB2000: Top sector MB84VB2001: Bottom sector * Embedded EraseTM Algorithms Automatically pre-programs and erases the chip or any sector * Embedded ProgramTM Algorithms Automatically writes and verifies data at specified address * Data Polling and Toggle Bit feature for detection of program or erase cycle completion * Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion * Automatic sleep mode When addresses remain stable, automatically switch themselves to low power mode. * Low VCC write inhibit 2.5 V * Erase Suspend/Resume Suspends the erase operation to allow a read data in another sector within the same device * Please refer to "MBM29LV800TA/BA" data sheet in detailed function
Embedded EraseTM and Embedded ProgramTM are trademarks of Advanced Micro Devices, Inc.
MB84VB2000-10/MB84VB2001-10
s BLOCK DIAGRAM
VCC VSS
A0 to A18 A-1 RESET CE1 BYTE 8 M bit Flash Memory
RY/BY
DQ0 to DQ15 VCC VSS
CE2
8 M bit Flash Memory
WE OE
2
MB84VB2000-10/MB84VB2001-10
s CONNECTION DIAGRAM
(Top View) A
6 5 4 3 2 1 N.C. A10 OE A11 A13 WE
B
VSS DQ5 DQ7 A8 A17 N.C.
C
DQ1 DQ2 DQ4 A5 CE2 A16
D
A1 A0 DQ0 DQ8 CE1 VSS
E
A2 A3 A6 DQ3 DQ10 DQ9
F
A4 A7 A18 DQ12 VCC DQ11
G
N.C. RY/BY RESET A12 DQ6 DQ13
H
A9 A14 A15 BYTE DQ15/A-1 DQ14
Table 1 MB84VB2000/MB84VB2001 Pin Configuration Pin A-1, A0 to A18 DQ0 to DQ15 CE1 CE2 OE WE RY/BY RESET BYTE N.C. VSS VCC Function Address Inputs (Common) Data Inputs/Outputs (Common) Chip Enable 1 Chip Enable 2 Output Enable (Common) Write Enable (Common) Ready/Busy Outputs (Common) Hardware Reset Pin/Sector Protection Unlock (Common) Selects 8-bit or 16-bit mode (Common) No Internal Connection Device Ground (Common) Device Power Supply (Common) Input/ Output I I/O I I I I O I I -- Power Power
3
MB84VB2000-10/MB84VB2001-10
s PRODUCT LINE UP
Part No. Ordering Part No. VCC = 3.0 V
+0.6 V -0.3 V
MB84VB2000/MB84VB2001 -10 100 100 40
Max. Address Access Time (ns) Max. CE Access Time (ns) Max. OE Access Time (ns)
s LOGIC SYMBOL
Table 2 Operation (5) Auto-Select Manufacture's Code (1) L H Auto-Select Device Code (1) L H Read (3) L Full Standby Output Disable Write (Program/Erase) L H Enable Sector Protection (2), (4) L H Verify Sector Protection (2), (4) L Temporary Sector Unprotection Reset (Hardware)/Standby X X H X X X X X X X X X X X X X X X HIGH-Z VID L H L L H L H L VID Code H H L VID L H L VID X H H X H H H X L H L A0 A1 A6 A9 DIN H X H X H X X X X X X X X HIGH-Z HIGH-Z H H H L L H A0 A1 A6 A9 DOUT H H L L H H L L VID Code H MB84VB2000/MB84VB2001 User Bus Operations (BYTE = VIH) CE1 H CE2 L L H L L L VID Code H OE WE A0 A1 A6 A9 DQ0 to DQ15 RESET
4
MB84VB2000-10/MB84VB2001-10
Table 3 Operation (5) Auto-Select Manufacture's Code (1) Auto-Select Device Code (1) L H Read (3) L Full Standby Output Disable Write (Program/Erase) L Enable Sector Protection (2), (4) Verify Sector Protection (2), (4) Temporary Sector Unprotection Reset (Hardware)/Standby H L H L X X H L VID H L L H X X X X X X X X X X X X X X X X X HIGH-Z VID L H L L H L VID Code H L L H L VID X H H X H H H X L H L A-1 A0 A1 A6 A9 DIN H X H X H X X X X X X X X X X HIGH-Z HIGH-Z H H H L L H A-1 A0 A1 A6 A9 DOUT H MB84VB2000/MB84VB2001 User Bus Operations (BYTE = VIL) CE1 H L H CE2 L L H L L H L H L L VID Code H H L L L L VID Code H OE WE DQ15/ A-1 A0 A1 A6 A9 DQ0 to DQ7 RESET
Legend: L = VIL, H = VIH, X = VIL or VIH,
= Pulse input. See DC Characteristics for voltage levels.
Notes: 1.Manufacturer and device codes may also be accessed via a command register write sequence. See Table 7. 2.Refer to the section on Sector Protection. 3.WE can be VIL if OE is VIL, OE at VIH initiates the write operations. 4.VCC = 3.3 V 10% 5.Do not apply CE1 = CE2 = VIL at a time.
5
MB84VB2000-10/MB84VB2001-10
s FLEXIBLE SECTOR-ERASE ARCHITECTURE
* One 16 K byte, two 8 K bytes, one 32 K byte, and fifteen 64 K bytes x 2. * Individual-sector, multiple-sector, or bulk-erase capability.
(x8) FFFFFH 16K byte/8K word FC000H 8K byte/4K word FA000H 8K byte/4K word F8000H 32K byte/16K word F0000H 64K byte/32K word E0000H 64K byte/32K word D0000H 64K byte/32K word C0000H 64K byte/32K word B0000H 64K byte/32K word A0000H 64K byte/32K word 90000H 64K byte/32K word 80000H 64K byte/32K word 70000H 64K byte/32K word 60000H 64K byte/32K word 50000H 64K byte/32K word 40000H 64K byte/32K word 30000H 64K byte/32K word 20000H 64K byte/32K word 10000H 64K byte/32K word 00000H MB84VB2000 Sector Architecture
(x16) 7FFFFH 64K byte/32K word 7E000H 64K byte/32K word 7D000H 64K byte/32K word 7C000H 64K byte/32K word 78000H 64K byte/32K word 70000H 64K byte/32K word 68000H 64K byte/32K word 60000H 64K byte/32K word 58000H 64K byte/32K word 50000H 64K byte/32K word 48000H 64K byte/32K word 40000H 64K byte/32K word 38000H 64K byte/32K word 30000H 64K byte/32K word 28000H 64K byte/32K word 20000H 32K byte/16K word 18000H 8K byte/4K word 10000H 8K byte/4K word 08000H 16K byte/8K word 00000H
(x8) FFFFFH F0000H E0000H D0000H C0000H B0000H A0000H 90000H 80000H 70000H 60000H 50000H 40000H 30000H 20000H 10000H 08000H 06000H 04000H 00000H MB84VB2001 Sector Architecture
(x16) 7FFFFH 78000H 70000H 68000H 60000H 58000H 50000H 48000H 40000H 38000H 30000H 28000H 20000H 18000H 10000H 08000H 04000H 03000H 02000H 00000H
6
MB84VB2000-10/MB84VB2001-10
s FUNCTIONAL DESCRIPTION
Table 4 Sector Address Tables (MB84VB2000) Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 A17 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 A16 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 A15 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 A14 X X X X X X X X X X X X X X X 0 1 1 1 A13 X X X X X X X X X X X X X X X X 0 0 1 A12 X X X X X X X X X X X X X X X X 0 1 X Address Range (x8) 00000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to F7FFFH F8000H to F9FFFH FA000H to FBFFFH FC000H to FFFFFH Address Range (x16) 00000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 77FFFH 78000H to 7BFFFH 7C000H to 7CFFFH 7D000H to 7DFFFH 7E000H to 7FFFFH
7
MB84VB2000-10/MB84VB2001-10
Table 5 Sector Address SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 A18 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A17 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A16 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A15 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Sector Address Tables (MB84VB2001) A14 0 0 0 1 X X X X X X X X X X X X X X X A13 0 1 1 X X X X X X X X X X X X X X X X A12 X 0 1 X X X X X X X X X X X X X X X X Address Range (x8) 00000H to 03FFFH 04000H to 05FFFH 06000H to 07FFFH 08000H to 0FFFFH 10000H to 1FFFFH 20000H to 2FFFFH 30000H to 3FFFFH 40000H to 4FFFFH 50000H to 5FFFFH 60000H to 6FFFFH 70000H to 7FFFFH 80000H to 8FFFFH 90000H to 9FFFFH A0000H to AFFFFH B0000H to BFFFFH C0000H to CFFFFH D0000H to DFFFFH E0000H to EFFFFH F0000H to FFFFFH Address Range (x16) 00000H to 01FFFH 02000H to 02FFFH 03000H to 03FFFH 04000H to 07FFFH 08000H to 0FFFFH 10000H to 17FFFH 18000H to 1FFFFH 20000H to 27FFFH 28000H to 2FFFFH 30000H to 37FFFH 38000H to 3FFFFH 40000H to 47FFFH 48000H to 4FFFFH 50000H to 57FFFH 58000H to 5FFFFH 60000H to 67FFFH 68000H to 6FFFFH 70000H to 77FFFH 78000H to 7FFFFH
8
MB84VB2000-10/MB84VB2001-10
Table 6.1 Flash Memory Autoselect Codes Type Manufacture's Code Byte MB84VB2000 Word Device Code Byte MB84VB2001 Word *1: A-1 is for Byte mode. VIL VIL VIH X 225BH VIL 5BH VIL VIL VIH X 22DAH A6 VIL A1 VIL A0 VIL A-1*1 VIL VIL Code (HEX) 04H DAH
Table 6.2 Expanded Autoselect Code Table Type Manufacture's Code (B) MB84VB2000 Device Code MB84VB2001 (W) (B): Byte mode (W): Word mode
225BH 0 0 1 0 0 0 1 0 0 1 0 1 1 0 1 1 Code DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1
04H A-1/0 DAH 22DAH 5BH A-1 0 A-1
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z 0 1 0 0 0 1 0
(W) (B)
HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z HI-Z
9
MB84VB2000-10/MB84VB2001-10
Table 7 Command Sequence Read/Reset Read/Reset Autoselect Program Chip Erase Sector Erase Flash Memory Command Definitions
Fourth Bus Bus First Bus Second Bus Third Bus Fifth Bus Sixth Bus Write Write Cycle Write Cycle Write Cycle Read/Write Write Cycle Write Cycle Cycle Cycles Req'd Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data 1 3 3 4 6 6 XXXH F0H 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH AAH AAH AAH AAH AAH -- 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H 2AAH 555H -- 55H 55H 55H 55H 55H -- 555H AAAH 555H AAAH 555H AAAH 555H AAAH 555H AAAH -- F0H 90H A0H 80H 80H -- RA -- PA 555H AAAH 555H AAAH -- RD -- PD AAH AAH -- -- -- -- 2AAH 555H 2AAH 555H -- -- -- -- 55H 55H -- -- -- -- 555H AAAH SA -- -- -- -- 10H 30H
Sector Erase Suspend Sector Erase Resume Set to Fast Mode Fast Program (Note) Reset from Fast Mode (Note) Extended Sector Protect 3 2 2 4
Erase can be suspended during sector erase with Addr. ("H" or "L"). Data (B0H) Erase can be resumed after suspend with Addr. ("H" or "L"). Data (30H) 555H AAAH XXXH XXXH XXXH XXXH XXXH AAH A0H 90H 60H 2AAH 555H PA XXXH XXXH SPA 55H PD F0H 60H 555H AAAH -- -- SPA 20H -- -- 40H -- -- -- SPA -- -- -- SD -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Address bits A11 to A17 = X = "H" or "L" for all address commands except or Program Address (PA) and Sector Address (SA). Bus operations are defined in Tables 2 and 3. The system should generate the following address patterns: Word Mode: 555H or 2AAH to addresses A0 to A10 Byte Mode: AAAH or 555H to addresses A-1 and A0 to A10 Both Read/Reset commands are functionally equivalent, resetting the device to the read mode. RA =Address of the memory location to be read PA =Address of the memory location to be programmed Addresses are latched on the falling edge of the write pulse. SA =Address of the sector to be erased. The combination of A18, A17, A16, A15, A14, A13, and A12 will uniquely select any sector. RD =Data read from location RA during read operation. PD =Data to be programmed at location PA. Data is latched on the falling edge of write pulse. SPA:Sector address to be protected. Set sector address (SA) and (A6, A1, A0) = (0, 1, 0). SD:Sector protection verify data. Output 01H at protected sector addresses and output 00H at unprotected sector addresses.
10
MB84VB2000-10/MB84VB2001-10
s ABSOLUTE MAXIMUM RATINGS
Storage Temperature .................................................................................................. -55C to +125C Ambient Temperature with Power Applied .................................................................. -25C to +85C Voltage with Respect to Ground All pins (Note) .......................................................... -0.3 V to VCC + 0.5 V VCCf/VCCs Supply (Note) .............................................................................................. -0.3 V to +4.6 V Note: Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitions, inputs may negative overshoot VSS to -2.0 V for periods of up to 20 ns. Maximum DC voltage on output and I/O pins are VCCf + 0.5 V or VCCs + 0.5 V. During voltage transitions, outputs may positive overshoot to VCC + 2.0 V for periods of up to 20 ns. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING RANGES
Commercial Devices Ambient Temperature (TA) .........................................................................-40C to +85C VCC Supply Voltages ..................................................................................+2.7 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. WARNING: Recommended operating conditions are normal operating ranges for the semiconductor device. All the device's electrical characteristics are warranted when operated within these ranges. Always use semiconductor devices within the recommended operating conditions. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representative beforehand.
11
MB84VB2000-10/MB84VB2001-10
s DC CHARACTERISTICS
Parameter Symbol ILI ILO ILIT Parameter Description Input Leakage Current Output Leakage Current A9, OE, RESET Inputs Leakage Current Test Conditions VIN = VSS to VCC, VCC = VCC Max. VOUT = VSS to VCC, VCC = VCC Max. VCC = VCC Max. A9, OE, RESET = 12.5 V CE = VIL, OE = VIH, f = 10 MHz ICC1 VCC Active Current (Note 1, 5) CE = VIL, OE = VIH, f = 5 MHz ICC2 ICC3 ICC4 VCC Active Current (Note 2, 5) VCC Current (Standby) (Note 5) VCC Current (Standby, Reset) (Note 5) VCC Current (Automatic Sleep Mode) (Note 3, 5) Input Low Level Input High Level Voltage for Autoselect and Sector Protection (A9, OE, RESET) (Note 4) Output Low Voltage Level Output High Voltage Level VOH2 VLKO Low VCC Lock-Out Voltage CE = VIL, OE = VIH VCC = VCC Max., CE = VCC 0.3 V, RESET = VCC 0.3 V VCC = VCC Max., RESET = VSS 0.3 V VCC = VCC Max., CE = VSS 0.3 V, RESET = VCC 0.3 V VIN = VCC 0.3 V or VSS 0.3 V -- -- -- IOL = 4.0 mA, VCC = VCC Min. IOH = -2.0 mA, VCC = VCC Min. IOH = -100 A, VCC = VCC Min. -- Byte -- Word -- -- -- 15 35 5 5 mA A A 12 mA Byte -- Word 25 Min. -1.0 -1.0 -- Max. +1.0 +1.0 70 22 mA Unit A A A
ICC5 VIL VIH VID VOL VOH1
-- -0.5 2.0 11.5 -- 2.4 VCC - 0.4 2.3
5 0.6 VCC + 0.3 12.5 0.45 -- -- 2.5
A V V V V V V V
Notes: 1.The ICC current listed includes both the DC operating current and the frequency dependent component (at 10 MHz). 2.ICC active while Embedded Algorithm (program or erase) is in progress. 3. Automatic sleep mode enables the low power mode when address remain stable for 150 ns. 4. (VID - VCC) do not exceed 9 V. 5. Total power consumption is (condition of Flash 1) + (condition of Flash 2).
12
MB84VB2000-10/MB84VB2001-10
s AC CHARACTERISTICS
* CE Timing Parameter Symbols JEDEC -- Standard tCCR CE Recover Time -- Min. 0 ns
Description
Test Setup
-10
Unit
* Read Only Operations Characteristics Parameter Symbols JEDEC tAVAV tAVQV tELQV tGLQV tEHQZ tGHQZ tAXQX -- -- Standard tRC tACC tCE tOE tDF tDF tOH tREADY tELFL tELFH Read Cycle Time Address to Output Delay Chip Enable to Output Delay Output Enable to Output Delay Chip Enable to Output High-Z Output Enable to Output High-Z Output Hold Time from Addresses, CE or OE, Whichever Occurs First RESET Pin Low to Read Mode CE or BYTE Switching Low or High -- CE = VIL OE = VIL OE = VIL -- -- -- -- -- -- Test Setup -10 (Note) Min. 100 -- -- -- -- -- 0 -- -- Max. -- 100 100 40 30 30 -- 20 5 ns ns ns ns ns ns ns s ns
Description
Unit
Note: Test Conditions-Output Load: 1 TTL gate and 30 pF Input rise and fall times: 5 ns Input pulse levels: 0.0 V to 3.0 V Timing measurement reference level Input: 1.5 V Output: 1.5 V
13
MB84VB2000-10/MB84VB2001-10
* Erase/Program Operations Parameter Symbols JEDEC tAVAV tAVWL tAVEL tWLAX tELAX tDVWH tWHDX -- -- tGHEL tGHWL tWLEL tELWL tEHWH tWHEH tWLWH tELEH tWHWL tEHEL tWHWH1 tWHWH2 -- -- -- -- -- -- -- -- -- -- -- -- -- Standard tWC tAS tAS tAH tAH tDS tDH tOES tOEH tGHEL tGHWL tWS tCS tWH tCH tWP tCP tWPH tCPH tWHWH1 tWHWH2 tVCS tVIDR tVLHT tWPP tOESP tCSP tRB tRP tRH tEOE tBUSY tFLQZ tFLQV Write Cycle Time Address Setup Time (WE to Addr.) Address Setup Time (CE to Addr.) Address Hold Time (WE to Addr.) Address Hold Time (CE to Addr.) Data Setup Time Data Hold Time Output Enable Setup Time Output Enable Hold Time Read Toggle and Data Polling Description -10 Min. 100 0 0 50 50 50 0 0 0 10 0 0 0 0 0 0 50 50 30 30 -- -- 50 500 4 100 4 4 0 500 200 -- -- -- 30 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 8 1 -- -- -- -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 15 -- -- -- -- -- -- -- -- -- 100 90 30 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s sec s ns s s s s ns ns ns ns ns ns ns
Read Recover Time Before Write (OE to CE) Read Recover Time Before Write (OE to WE) WE Setup Time (CE to WE) CE Setup Time (WE to CE) WE Hold Time (CE to WE) CE Hold Time (WE to CE) Write Pulse Width CE Pulse Width Write Pulse Width High CE Pulse Width High Byte Programming Operation Sector Erase Operation (Note 1) VCC Setup Time Rise Time to VID (Note 2) Voltage Transition Time (Note 2) Write Pulse Width (Note 2) OE Setup Time to WE Active (Note 2) CE Setup Time to WE Active (Note 2) Recover Time from RY/BY RESET Pulse Width RESET Hold Time Before Read Delay Time from Embedded Output Enable Program/Erase Valid to RY/BY Delay BYTE Switching Low to Output High-Z BYTE Switching High to Output Active
Notes: 1. This does not include the preprogramming time. 2. This timing is for Sector Protection operation. 14
MB84VB2000-10/MB84VB2001-10
s SWITCHING WAVEFORMS
CE1
tCCR
tCCR
CE2
Figure 1
Timing Diagram for Alternating Flash to Flash
15
MB84VB2000-10/MB84VB2001-10
tRC
Addresses
tACC
Addresses Stable
CE
tOE tDF
OE
tOEH
WE
tCE
DQ
HIGH-Z
Output Valid
HIGH-Z
tRC
Addresses
tACC tRH
Addresses Stable
RESET
tOH
DQ
HIGH-Z
Output Valid
Figure 2
AC Waveforms for Read Operations
16
MB84VB2000-10/MB84VB2001-10
3rd Bus Cycle Addresses
555H tWC tAS PA tAH
Data Polling
PA tRC
CE CE
tCS tCH tCE
OE OE
tGHWL tWP tWPH tWHWH1 tOE
WE WE
tDS tDH tOH
Data
A0H
PD
DQ7 DQ7
DOUT
DOUT
Notes: 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at byte address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. 6.These waveforms are for the x16 mode. (The addresses differ from x8 mode.) Figure 3 Alternate WE Controlled Program Operation Timings
17
MB84VB2000-10/MB84VB2001-10
3rd Bus Cycle
Data Polling Data Polling
Addresses
555H tWC tAS
PA tAH
PA
WE
tWS tWH
OE
tGHEL tCP tCPH tWHWH1
CE
tDS tDH
Data
A0H
PD
DQ7
DOUT
Notes: 1.PA is address of the memory location to be programmed. 2.PD is data to be programmed at byte address. 3.DQ7 is the output of the complement of the data written to the device. 4.DOUT is the output of the data written to the device. 5.Figure indicates last two bus cycles out of four bus cycle sequence. 6.These waveforms are for the x16 mode. (The addresses differ from x8 mode.)
Figure 4
Alternate CE Controlled Program Operation Timings
18
MB84VB2000-10/MB84VB2001-10
Addresses
555H tWC
2AAH tAS tAH
555H
555H
2AAH
SA*
CE CE
tCS tCH
OE OE
tGHWL tWP tWPH
WE WE
tDS AAH
tDH 55H 80H AAH 55H 10H/ 30H
Data
tVCS
VCC
* : SA is the sector address for Sector Erase. Addresses = 555H (Word), AAAH (Byte) for Chip Erase. Note: These waveforms are for the x 16 mode. (The addresses differ from x 8 mode.) Figure 5 AC Waveforms Chip/Sector Erase Operations
19
MB84VB2000-10/MB84VB2001-10
CE CE
tCH tOE tDF
OE OE
tOEH
WE WE
tCE
* DQ7
Data
DQ7 DQ7
DQ7 = Valid Data
High-Z
tWHWH1 or 2
DQ0 to DQ6
Data
DQ0 to DQ6 = Output Flag tEOE
DQ0 to DQ6 Valid Data
High-Z
* : DQ7 = Valid Data (The device has completed the Embedded operation.) Figure 6 AC Waveforms for Data Polling during Embedded Algorithm Operations
CE CE
tOEH
WE WE
tOES
OE OE
*
DQ6
Data
DQ6 = Toggle
DQ6 = Toggle
tOE
DQ6 = Stop Toggling
Valid
* : DQ6 stops toggling.(The device has completed the Embedded operation.) Figure 7 AC Waveforms for Toggle Bit during Embedded Algorithm Operations
20
MB84VB2000-10/MB84VB2001-10
CE CE
The rising edge of the last WE signal The rising edge of the last WE signal
WE WE
Entire programming or erase operations
RY/BY
tBUSY
Figure 8
RY/BY Timing Diagram during Write/Erase Operations
WE WE
RESET RESET
tRP tRB
RY/BY
tREADY
Figure 9
RESET, RY/BY Timing Diagram
21
MB84VB2000-10/MB84VB2001-10
CE
BYTE
Data Output (DQ0 to DQ7) tELFH tFHQV A-1 DQ15 Data Output (DQ0 to DQ14)
DQ0 to DQ14
DQ15/A-1
Figure 10
Timing Diagram for Word Mode Configuration
CE
BYTE
tELFL
DQ0 to DQ14
Data Output (DQ0 to DQ14)
Data Output (DQ0 to DQ7)
DQ15/A-1
DQ15 tFLQZ
A-1
Figure 11
Timing Diagram for Byte Mode Configuration
The falling edge of the last WE signal
CE or WE
BYTE
tSET (tAS)
Input Valid tHOLD (tAH)
Figure 12
BYTE Timing Diagram for Write Operations
22
MB84VB2000-10/MB84VB2001-10
A18, A17, A16 A15, A14 A13, A12 A0
SAX
SAY
A1
A6
12 V 3V A9
tVLHT
12 V 3V OE OE
tVLHT tWPP
tVLHT
tVLHT
WE WE
tOESP
CE CE
tCSP
Data
tVCS tOE
01H
VCC
SAX : Sector Address for initial sector SAY : Sector Address for next sector Note: A-1 is VIL on byte mode. Figure 13 AC Waveforms for Sector Protection Timing Diagram
23
MB84VB2000-10/MB84VB2001-10
FAST MODE ALGORITHM
Start
RESET = VID
Wait to 4 s
Device is Operating in Temporary Sector Unprotection Mode
No
Extended Sector Protection Entry? Yes To Setup Sector Protection Write XXXH/60H
PLSCNT = 1
To Sector Protection Write SPA/60H (A0 = VIL, A1 = VIH, A6 = VIL)
Increment PLSCNT
Time Out 150 s
To Verify Sector Protection Write SPA/40H (A0 = VIL, A1 = VIH, A6 = VIL)
Setup Next Sector Address
Read from Sector Address (A0 = VIL, A1 = VIH, A6 = VIL) No No PLSCNT = 25? Yes Remove VID from RESET Write Reset Command Data = 01H? Yes Protection Other Sector ? No Remove VID from RESET Write Reset Command Yes
Device Failed
Sector Protection Completed
Figure 14
Extended Sector Protection Algorithm
24
MB84VB2000-10/MB84VB2001-10
VCC tVCS 12 V 3V RESET
tVIDR tVLHT
3V
CE CE
WE
WE
tVLHT RY/BY RY/BY
Program or Erase Command Sequence
tVLHT
Figure 15
Temporary Sector Unprotection Timing Diagram
Enter Embedded Erasing WE WE
Erase Suspend Erase
Enter Erase Suspend Program Erase Suspend Program
Erase Resume Erase Suspend Read Erase Erase Complete
Erase Suspend Read
DQ6
DQ2
Toggle Toggle DQ2 and DQ6 DQ2 and DQ6 with OE with OE
Note: DQ2 is read from the erase-suspended sector. Figure 16 DQ2 vs DQ6
25
MB84VB2000-10/MB84VB2001-10
s ERASE AND PROGRAMMING PERFORMANCE
Limits Parameter Min. Sector Erase Time Word Programming Time Byte Programming Time Chip Programming Time (1M Byte) Erase/Program Cycle -- -- -- -- 100,000 Typ. 1 16 8 8.4 -- Max. 15 5,200 3,600 50 -- sec s s sec cycles Excludes programming time prior to erasure Excludes system-level overhead Excludes system-level overhead Unit Comments
s PIN CAPACITANCE
Parameter Symbol CIN COUT CIN2 Parameter Description Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ. TBD TBD TBD Max. TBD TBD TBD Unit pF pF pF
Note: Test conditions TA = 25C, f = 1.0 MHz
s HANDLING OF PACKAGE
Please hadle this package carefully since the sides of package are right angle.
26
MB84VB2000-10/MB84VB2001-10
s PACKAGE
48-pin plastic FBGA
(BGA-48P-M06)
s PACKAGE DIMENSIONS
48-pin plastic BGA (BGA-48P-M06) Note: The actual shape of corners may differ from the dimension.
11.000.15(.433.006)
1.400.20 (.055.008) 0.300.10 (.012.004)
7.000.15(.276.006)
10.000.15 (.394.006)
O0.400.10 (O.016.004)
5.000.15 (.197.006)
0.15(.006) 1st PIN
INDEX
1.000.15 (.039.006)
INDEX
Dimension in mm (inches).
C
1998 FUJITSU LIMITED MCM-M001-2-3
27
MB84VB2000-10/MB84VB2001-10
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: (044) 754-3763 Fax: (044) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9804 (c) FUJITSU LIMITED Printed in Japan
28

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